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Solving the next parasitic extraction challenge
The Semiconductor Technology Roadmap [1] describes the problems that need to be tackled for future generations of silicon technology. The report illustrates the electrical and manufacturing...
View ArticleDAC 2012: 20(nm) questions
Although there has been a lot of angst expressed about the future of IC scaling, the folks in the trenches are hard at work making sure 20nm is ready for design starts. One of the big stories at DAC...
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Critical tools for 20nm design
The shift to 20nm processes is expected to halve the area used to put a given function on chip, and to offer designers a choice of either halving the design’s power consumption or increasing its...
View ArticleClik here to view.
How to design with finFETs
The finFET (Guide) is being promoted as the basic device for future IC processes, now that the scaling of planar transistors is no longer bringing the performance and power-consumption advantages to...
View ArticleFinFET parasitics come under control
The introduction of finFET processes marks the first time that the CMOS transistor has had to be considered as a truly three-dimensional (3D) device, with all the complexity and uncertainty that this...
View ArticleClik here to view.
Full 3D-IC parasitic extraction
3D IC design is gaining a great deal of interest. It promises device scaling at minimized cost within manageable form factors. But there remains the challenge of verifying components produced on...
View ArticleParasitic extraction
Parasitic extraction tools help designers understand how physical implementation will impact the behavior of their ideal logic and circuits, by analyzing the layout of their design and calculating the...
View ArticleDealing with parasitic-extraction challenges in finFETs and advanced nodes
The emergence of finFETs and 3DICs at advanced nodes provide welcome shots in the arm for electronics design productivity. The benefits, however, don’t come without their challenges, particularly early...
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Hierarchical signoff of SoC designs at advanced process nodes
Advanced node SoCs integrate hundreds of functional blocks to achieve the rich features required from today’s electronics. As these designs grow to hundreds of millions of instances and their product...
View ArticleDAC 2012: 20(nm) questions
Although there has been a lot of angst expressed about the future of IC scaling, the folks in the trenches are hard at work making sure 20nm is ready for design starts. One of the big stories at DAC...
View ArticleClik here to view.
Critical tools for 20nm design
The shift to 20nm processes is expected to halve the area used to put a given function on chip, and to offer designers a choice of either halving the design’s power consumption or increasing its...
View ArticleClik here to view.
How to design with finFETs
The finFET (Guide) is being promoted as the basic device for future IC processes, now that the scaling of planar transistors is no longer bringing the performance and power-consumption advantages to...
View ArticleFinFET parasitics come under control
The introduction of finFET processes marks the first time that the CMOS transistor has had to be considered as a truly three-dimensional (3D) device, with all the complexity and uncertainty that this...
View ArticleClik here to view.
Full 3D-IC parasitic extraction
3D IC design is gaining a great deal of interest. It promises device scaling at minimized cost within manageable form factors. But there remains the challenge of verifying components produced on...
View ArticleParasitic extraction
Parasitic extraction tools help designers understand how physical implementation will impact the behavior of their ideal logic and circuits, by analyzing the layout of their design and calculating the...
View ArticleDealing with parasitic-extraction challenges in finFETs and advanced nodes
The emergence of finFETs and 3DICs at advanced nodes provide welcome shots in the arm for electronics design productivity. The benefits, however, don’t come without their challenges, particularly early...
View ArticleClik here to view.
Hierarchical signoff of SoC designs at advanced process nodes
Advanced node SoCs integrate hundreds of functional blocks to achieve the rich features required from today’s electronics. As these designs grow to hundreds of millions of instances and their product...
View ArticleClik here to view.
Today’s analog/RF designs need interconnect inductance extraction
Mobile networking and wireless communications are essential technologies. From smartphones to the Internet of things (IoT), we have created an environment that relies on interconnectivity. We...
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